1. Field of the Invention
The present invention relates to an IC measuring device for testing an IC (particularly an IC containing data strobe).
2. Description of the Related Art
FIG. 5 is a block diagram showing the configuration of a background-art IC measuring device. FIG. 6 is a timing chart showing the operation of the IC measuring device. First, an IC measuring device (A1) supplies a clock (CK1) to an IC (B1) to be measured. Thus, the IC (B1) to be measured is operated in synchronism with a test cycle (TC1) having a period corresponding to the clock (CK1).
The output timing at which a data strobe (DCK1) is outputted from the IC (B1) to be measured is supplied to an edge search circuit (E11) in a logic comparator (CMP11) through a voltage comparator (V11) in the IC measuring device (A1). The edge search circuit (E11) latches the data strobe (DCK1) at the timing of a judgment strobe pulse (S11) outputted from a timing generator (TG11). The timing of the edge of the judgment strobe pulse (S11) outputted from the timing generator (TG11) is varied n times every test cycle (TC1) within a range of from a time point T21 to a time point T22. That is, time corresponding to n cycles of the test cycle (TC1) is required for varying the timing n times.
The logic comparator (CMP11) latches the state of the data strobe (DCK1) at the timing of the edge of the judgment strobe pulse (S11), and compares the state of the data strobe (DCK1) with an expected value (K11). That is, the state of the data strobe (DCK1) is latched and compared with the expected value (K11) while the timing of the edge of the judgment strobe pulse (S11) is varied n times. Thus, the timing at which the edge of the data strobe (DCK1) is outputted is detected, that is, an interval between a time point T11 when the leading edge of the clock (CK1) is outputted and a time point when the edge of the data strobe (DCK1) is outputted is detected.
Similarly, while the timing of the edge of a judgment strobe (S12) is varied, the timing at which the edge of data (D11) is outputted is detected, that is, an interval between the time point T11 when the leading edge of the clock (CK1) is outputted and a time point when the edge of the data (D11) is outputted is detected.
Then, a difference between the two intervals is obtained, and PASS/FAIL of the measured IC (B11) is judged.
In the above-mentioned background art, the operation of latching the state of the data strobe (DCK1) at the timing of the edge of the judgment strobe pulse (S11) and comparing the state of the data strobe (DCK1) with the expected value (K11) is required to be repeated n times so as to detect the timing at which the edge of the data strobe (DCK1) is outputted.
Similarly, the operation of latching the state of the data (D11) at the timing of the edge of the judgment strobe pulse (S12) and comparing the state of the data (D11) with an expected value (K12) must be repeated n times so as to detect the timing at which the edge of the data (D1) is outputted.
Further, if data outputted from the IC (B1) to be measured do not include only the data (D11) but include a plurality of data, for example, data (D11), data (D12), . . . , the above-mentioned comparison operation repeated n times must be repeated in accordance with the number of data in order to detect the respective timings of the data. That is, when the number of data is k, the above-mentioned operation of latch and comparison must be repeated k×n times.
That is, in the above-mentioned background art, there is a problem that it takes much time to measure the timing at which the IC (B1) to be measured outputs data (a data strobe or data) to be measured.
In addition, in the background art, when the data strobe (DCK1) or the data (D11) varies in each test cycle (TC1), conclusion can be drawn only when the data strobe (DCK1) or the data (D11) is the slowest, and conclusion cannot be drawn for each test cycle.